پاورپوینت معماري کامپيوتر- درس نهم

پاورپوینت معماري کامپيوتر- درس نهم

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فرمت فایل اصلی: PowerPoint (pptx) (قابل ویرایش و آماده پرینت)
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پاورپوینت معماري کامپيوتر- درس نهم (pptx) 29 اسلاید

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نوع فایل : PowerPoint (.pptx) ( قابل ویرایش و آماده پرینت )

تعداد اسلاید: 29 اسلاید

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معماري کامپيوتر- درس نهمpipelineبرگرفته از درس :Prof. David A. PattersonPipelining: Its Natural!Laundry ExampleAnn Brian Cathy Daveeach have one load of clothesto wash dry and foldWasher takes 30 minutesDryer takes 40 minutes“Folder” takes 20 minutesSequential LaundrySequential laundry takes 6 hours for 4 loadsIf they learned pipelining how long would laundry take? 3040203040203040203040206 PM7891011MidnightTaskOrderTimePipelined LaundryPipelined laundry takes 3.5 hours for 4 loads 6 PM7891011MidnightTaskOrderTimePipelining LessonsPipelining doesn’t help latency of single task it helps throughput of entire workloadPipeline rate limited by slowest pipeline stageMultiple tasks operating simultaneouslyPotential speedup = Number pipe stagesUnbalanced lengths of pipe stages reduces speedupTime to “fill” pipeline and time to “drain” it reduces speedup6 PM789TaskOrderTimeComputer PipelinesExecute billions of instructions so throughput is what mattersWhat is desirable in instruction sets for pipelining?Variable length instructions vs.all instructions same length?Memory operands part of any operation vs. memory operands only in loads or stores?Register operand many places in instruction format vs. registers located in same place?A "Typical" RISC32-bit fixed format instruction (3 formats)Memory access only via load/store instructions32 32-bit GPR 3-address reg-reg arithmetic instruction; registers in same placeSingle address mode for load/store:base + displacementno indirectionSimple branch conditionsDelayed branchsee: SPARC MIPS HP PA-Risc DEC Alpha IBM PowerPC CDC 6600 CDC 7600 Cray-1 Cray-2 Cray-35 Steps of MIPS DatapathFigure 3.1 Page 130 CA:AQA 2eMemoryAccessWriteBackInstructionFetchInstr. DecodeReg. FetchExecuteAddr. CalcLMDMUXMemoryReg FileMUXMUXDataMemoryMUXSignExtendZero?Next SEQ PCNext PCWB DataRDRS1RS2Imm5 Steps of MIPS DatapathFigure 3.4 Page 134 CA:AQA 2eMemoryAccessWriteBackInstructionFetchInstr. DecodeReg. FetchExecuteAddr. CalcMemoryReg FileMUXMUXDataMemoryMUXSignExtendZero?Next SEQ PCNext SEQ PCRDRDRDWB Data Data stationary control local decode for each instruction phase / pipeline stageNext PCRS1RS2ImmMUX